TSMC zároveň ve spolupráci s partnery a vědeckými týmy z různých univerzit (NTU, MIT) vyvinulo jednu z klíčových technologií pro 1nm výrobu, která by mohla být zahájena kolem roku 2025.<ref>[https://www.zive.cz/clanky/tsmc-a-vedci-vyvinuli-klicovou-technologii-pro-1nm-vyrobu-cipu/sc-3-a-210249/default.aspx Karel Javůrek, TSMC a vědci vyvinuli klíčovou technologii pro 1nm výrobu čipů, Živě, 21.5.2021]</ref>
** 0.13 μm (options: general-purpose (G), low-power (LP), high-performance low-voltage (LV)).
** 90 nm (based upon 80GC from Q4/2006),
** 65 nm (options: general-purpose (GP), low-power (LP), ultra-low power (ULP), LPG).
** 55 nm (options: general-purpose (GP), low-power (LP)).
** 40 nm (options: general-purpose (GP), low-power (LP), ultra-low power (ULP)).
** 28 nm (options: high-performance (HP), high-performance mobile (HPM), high-performance computing (HPC), high-performance low-power (HPL), low-power (LP), high-performance computing Plus (HPC+), ultra-low power (ULP)) with HKMG.
** 22 nm (options: ultra-low power (ULP), ultra-low leakage (ULL))
** 20 nm
** 16 nm (options: FinFET (FF), FinFET Plus (FF+), FinFET Compact (FFC))
** 12 nm (options: FinFET Compact (FFC), FinFET NVIDIA (FFN)), enhanced version of 16 nm process.
** 10 nm (options: FinFET (FF))
** 7 nm (options: FinFET (FF), FinFET Plus (FF+), FinFET Pro (FFP), high-performance computing (HPC))
** 6 nm (options: FinFET (FF)), enhanced version of 7 nm process.
** 5 nm (options: FinFET (FF)).
== Zisky ==
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